The present invention relates to a semiconductor integrated circuit with a dynamic random-access memory (DRAM).
Recently, an LSI, in which a logic circuit, like a central processing unit (CPU) or application-specific integrated circuit (ASIC), and a DRAM have been integrated together on a single semiconductor substrate, has been the object of much attention. In the following description, a semiconductor integrated circuit of this type will be referred to as a xe2x80x9cDRAM-built-in LSIxe2x80x9d, which is also called an xe2x80x9cLSI with an embedded DRAMxe2x80x9d. A DRAM-built-in LSI is attractive, because an LSI of this type realizes various functions, which have had to be executed using multiple chips including logic and general-purpose DRAM chips, by a single chip.
For a DRAM-built-in LSI, there is no need to interconnect multiple chips together by way of long wires. In addition, the same bonding pad can be used for both the logic and memory circuits alike. Accordingly, the LSI occupies a smaller area when mounted on a circuit board. Furthermore, the shorter wire length contributes to decreasing the wiring capacitance and increasing the data transfer rate. Moreover, no drivers of a great size are needed anymore because those long wires can be eliminated. As a result, the power dissipation of the overall system can be reduced advantageously.
Hereinafter, a typical known DRAM-built-in LSI, including a stacked capacitor DRAM, will be described. In the LSI of this type, its logic circuit is implemented as a complementary metal-oxide semiconductor (CMOS) circuit.
FIG. 8 is a cross-sectional view schematically illustrating a structure for a known DRAM-built-in LSI including a stacked capacitor DRAM. The LSI shown in FIG. 8 includes p-type semiconductor substrate (p-SUB) 91, n-wells (NWs) 92 and 94, p-well (PW) 93, n-channel MOS (NMOS) memory access transistor 95, stacked memory cell capacitor 96 and NMOS and p-channel MOS (PMOS) transistors 97 and 98 for a logic circuit.
As shown in FIG. 8, the NWs 92 and 94 and the PW 93 have been defined in the p-SUB 91. Multiple n+- and p+-type doped regions have also been defined in the p-SUB 91. The NMOS memory access transistor 95 is connected to a data line BL and a word line WL. A supply voltage VDD is applied to the NWS 92 and 94, while a substrate bias voltage VBB, lower than the ground voltage, is applied to the PW 93.
In a DRAM-built-in LSI in general, the transistors and capacitors thereof are downsized to increase the operating speed of its logic circuit, and the transistors are integrated together highly densely in its DRAM to reduce the necessary chip area. As shown in FIG. 8, an NMOS transistor is used as the memory access transistor 95. On the other hand, the memory cell capacitor 96 has a three-dimensional structure (e.g., implemented as a stacked type) to produce a capacitance large enough to stabilize the operation of the DRAM. Furthermore, the PW 93 is included in the NW 92 that has been defined in the p-SUB 91, thus forming a so-called xe2x80x9ctriple well structurexe2x80x9d.
The PW 93, NW 92 and p-SUB 91 are supplied with such voltages that will make their pn junctions reverse biased.
Specifically, the p-SUB 91, NW 92 and PW 93 are biased to the ground voltage, the supply voltage VDD and a negative voltage VBB, which is lower than the ground voltage, respectively. The voltages VDD and VBB are output from a power supply circuit (not shown) formed on the p-SUB 91.
By forming the memory access transistor 95 and memory cell capacitor 96 over the triple well structure and by biasing those wells to these levels, the memory and logic circuits can be electrically isolated from each other. In addition, the threshold voltage of the memory access transistor 95 is set high enough so that the charges stored on the memory cell capacitor 96 do not leak into the data line BL by way of the memory access transistor 95.
The voltage on the data line BL will be somewhere between the ground voltage and the supply voltage VDD. To read or write data from/on the memory cell capacitor 96, a voltage higher than the supply voltage VDD by the threshold voltage of the memory access transistor 95 should be applied to the gate electrode of the transistor 95. Accordingly, either a voltage generated by an internal booster or an externally in-put voltage should be applied onto the word line WL.
In the logic circuit section on the other hand, the NMOS and PMOS transistors 97 and 98, existing over the p-SUB 91 and NW 94, respectively, form part of a CMOS logic circuit. In the CMOS logic circuit, the NMOS and PMOS transistors 97 and 98 operate mutually complementarily. Since the p-SUB 91 is biased to the ground voltage, the threshold voltage does not increase or the operating speed does not decrease.
A DRAM-built-in LSI of this type, however, requires a fabrication process much more complicated than a normal CMOS process. Also, a greater number of process steps or masks are needed, thus raising the fabrication costs disadvantageously. For example, the process steps of forming the triple well structure and forming the stacked memory cell capacitor should be carried out in addition to those of a normal CMOS process.
Moreover, where the stacked capacitor is formed over the data line, the upper electrode thereof should be located at a rather high level, thus increasing the aspect ratio of a via that connects the first- and second-level interconnects together. Accordingly, it is much more difficult to form such an interconnect structure. Furthermore, after the transistors have been formed for the CMOS logic circuit, a capacitive insulating film should be formed at an elevated temperature for the stacked capacitor. Thus, the transistors of the CMOS logic circuit might have their performance degraded.
Furthermore, a charge-pump-type voltage step-up power supply circuit should be provided to apply the voltage, higher than the supply voltage VDD, as a word line drive voltage. A charge-pump-type negative voltage power supply circuit should also be provided to bias the well, on which the memory cell will be formed, to the voltage lower than the ground voltage. These charge-pump-type power supply circuits, however, often cause a great, inconstant variation in the voltage supplied. This is a problem inevitable for the power supply circuits of this type due to their constructions. Accordingly, not so great a margin is allowable for the voltage or temperature range in which the DRAM can operate stably enough.
Considering the compatibility with the CMOS process, it would be more advantageous to integrate a static random-access memory (SRAM), not the DRAM, with the CMOS logic circuit on the same semiconductor substrate. However, a normal six-transistor SRAM cell is greater in area than a DRAM cell almost tenfold. Accordingly, the SRAM would require a much greater chip area. Consequently, even in compliance with the currently minimum possible design rule of 0.18 xcexcm, for example, the SRAM built in the chip can have a storage capacity of just several hundreds kilobits at most.
In contrast, a DRAM cell is much smaller in area than an SRAM cell. Thus, a great number of DRAM cells can be integrated together on a single chip. That is to say, a CMOS logic circuit and a DRAM with a large storage capacity can be integrated together on a small-area chip. However, the known DRAM-built-in LSI requires a much higher process cost and likely results in performance degradation of the CMOS logic circuit thereof as described above. Accordingly, the effective applications of the known DRAM-built-in LSI are virtually limited to transferring an enormous quantity of data at a high speed by using a DRAM that has a rather great storage capacity and a bus of a broad enough bit width (e.g., graphics applications).
On the other hand, there are many applications requiring a memory with a storage capacity of about 1 to 4 megabits, which may be regarded as a xe2x80x9cmedium capacityxe2x80x9d in accordance with the minimum design rule of 0.18 xcexcm. Accordingly, demand for integrating a medium-capacity memory, which needs a much smaller chip area than an SRAM with a similar capacity, along with a high-performance logic circuit on the same chip at a low cost has been on the rise.
It is therefore an object of the present invention to provide a semiconductor integrated circuit, including a stably operating DRAM, at a low cost.
Specifically, an inventive semiconductor integrated circuit includes: a first n-well defined in a p-type semiconductor region; word lines; data lines; and a dynamic randomaccess memory (DRAM) array. In the DRAM array, multiple memory cells are arranged in matrix over the first n-well. Each said memory cell includes a p-channel metal-oxide semiconductor (MOS) access transistor and a capacitor. The access transistor has its gate connected to an associated one of the word lines, its source connected to an associated one of the data lines and its drain connected to the capacitor. The integrated circuit further includes: a row of sense amplifiers coupled to the data lines; a word line driver for driving the word lines; and a power supply circuit. The power supply circuit receives an external supply voltage, generates internal supply voltages by stepping down the external supply voltage and then applies the internal supply voltages to the sense amplifiers, the word line driver and the first n-well.
In the inventive integrated circuit, the power supply circuit steps down the external supply voltage. Accordingly, there is no need to use any charge pump circuit that cannot operate stably enough due to its own circuit configuration. Instead, a voltage, generated by a voltage step-down circuit that realizes high-speed response and can supply a large current at a time, can be applied as an internal supply voltage to the sense amplifiers, for example. Thus, the memory array can operate stably enough.
In one embodiment of the present invention, the integrated circuit preferably further includes a logic circuit that has been formed in the p-type semiconductor region.
In such an embodiment, memory and logic circuits are formed on the same semiconductor substrate. Thus, the overall circuit area can be reduced and data can be transferred from the memory circuit to the logic circuit, or vice versa, at an increased rate.
In another embodiment of the present invention, the power supply circuit may step down the external supply voltage to generate primary and secondary internal supply voltages as the internal supply voltages. The primary internal supply voltage may be lower than the external supply voltage, while the secondary internal supply voltage may be lower than the external supply voltage but higher than the primary internal supply voltage. The primary internal supply voltage may be applied to the sense amplifiers, while the first n-well may be biased to the secondary internal supply voltage.
Then, the substrate can be biased in such a manner that the access transistor of each memory cell can have its threshold voltage raised and that the charges stored on the capacitor of the memory cell will not leak into the data line by way of the access transistor. In addition, the junction capacitance also decreases, so it is possible to reduce the parasitic capacitance associated with the data line. Accordingly, even if just a small quantity of charges have been stored on the capacitor of a memory cell, the memory cell still can be read accurately. That is to say, a broader margin is allowable for the operation range of the memory.
In this particular embodiment, the integrated circuit preferably further includes: a second n-well defined in the p-type semiconductor region; and a logic circuit. The logic circuit preferably includes: an n-channel MOS transistor formed in the p-type semiconductor region; and a p-channel MOS transistor formed in the second n-well. The power supply circuit preferably biases the second n-well to the primary internal supply voltage.
Then, memory array and CMOS logic circuit can be formed on the same semiconductor substrate without using the triple well structure. As a result, the fabrication process can be simplified.
Specifically, the capacitor of each said memory cell preferably includes: a planar insulating film formed over the first n-well; and a planar upper electrode formed over the planar insulating film and biased to a ground voltage.
Then, the memory cell can be made without performing any complicated process for forming a stacked or trenched capacitor. In addition, a capacitive insulating film for the capacitor of each memory cell can be made of an insulator with a dielectric constant higher than that of silicon dioxide. Accordingly, the capacitance per unit area can be increased for the capacitor, so the memory cell including that capacitor may have a smaller area. As a result, the fabrication cost can be cut down.
More specifically, the planar insulating film is preferably a silicon dioxide film that is almost as thick as the gate oxide film of the n- and p-channel MOS transistors.
In such an embodiment, the gate oxide film of transistors for a CMOS logic circuit and the capacitive insulating film of capacitors for memory cells can be formed in a single process step. Accordingly, a CMOS logic circuit and a DRAM array can be. formed on the same semiconductor substrate through a completely standard CMOS process, thus cutting down the fabrication cost. In addition, while the DRAM array is being formed for a semiconductor integrated circuit, the CMOS logic circuit does not have its performance degraded.
In still another embodiment, the power supply circuit may include a first MOS transistor and a first differential amplifier. The first MOS transistor may be interposed between an external supply voltage terminal and a first output terminal. The external supply voltage is applied through the external supply voltage terminal. The first differential amplifier may receive a first reference voltage and a voltage at the first output terminal. The power supply circuit may control the first MOS transistor by the output of the first differential amplifier. Also, the power supply circuit may set the primary internal supply voltage at a substantially constant voltage in accordance with the first reference voltage and output the primary internal supply voltage through the first output terminal.
Then, the power supply circuit can apply a constant primary internal supply voltage, which does not change depending on the external supply voltage, to various peripheral circuits (e.g., sense amplifiers) of the memory array. Thus, the memory can operate stably enough with a broader operation margin allowed against a variation in the external supply voltage.
In this particular embodiment, the power supply circuit preferably further includes a first reference voltage generator for generating the first reference voltage. The first reference voltage generator preferably includes a first fuse and regulates the first reference voltage by trimming the first fuse.
Then, the output voltage of the power supply circuit is regulable by trimming the fuse when the memory is tested after the integrated circuit has been fabricated. Thus, a constant voltage can be output without being affected by any process-related variation. That is to say, the memory can operate stably enough with a great margin allowed against the process-related variations. In addition, it is also possible to optimize the output voltage of the power supply circuit and stabilize the memory operation according to how much the characteristic value of the transistors has changed with the process-related variations.
Alternatively, the power supply circuit may further include a second MOS transistor and a second differential amplifier. The second MOS transistor may be interposed between the external supply voltage terminal and a second output terminal. The second differential amplifier may receive a second reference voltage and a voltage at the second output terminal. The power supply circuit may control the second MOS transistor by the output of the second differential amplifier. Also, the power supply circuit may set the secondary internal supply voltage at a substantially constant voltage corresponding to the second reference voltage and output the secondary internal supply voltage through the second output terminal.
Then, the power supply circuit can output a constant secondary internal supply voltage that does not change depending on the external supply voltage. Generally speaking, a voltage step-down circuit has higher current supplying ability and higher response speed than a voltage step-up circuit. Accordingly, if the first n-well is biased to this secondary internal supply voltage, a variation in voltage at the first n-well, resulting from a substrate current produced during the memory operation, can be minimized. As a result, the memory array can operate stably enough.
Specifically, in this case, the power supply circuit preferably generates the second reference voltage based on the primary internal supply voltage.
optionally, the power supply circuit may further include a second reference voltage generator for generating the second reference voltage. The second reference voltage generator may include a second fuse and regulate the second reference voltage by trimming the second fuse.
In yet another embodiment, the power supply circuit may step down the external supply voltage to generate primary and secondary internal supply voltages as the internal supply voltages. The primary internal supply voltage may be lower than the external supply voltage, while the secondary internal supply voltage may be lower than the external supply voltage but higher than the primary internal supply voltage. The primary internal supply voltage may be applied to the sense amplifiers, while the secondary internal supply voltage may be applied to the word line driver. The sense amplifiers may supply the primary internal supply voltage as a high-level voltage to the data lines. The word line driver may supply the secondary internal supply voltage as a non-selected-state voltage to the word lines.
In such an embodiment, when a memory cell is non-selected to store charges thereon, the access transistor of the memory cell has its gate voltage raised. Then, the sub-threshold current can be reduced drastically and the leakage of the charges from the capacitor into the data line by way of the access transistor can be minimized. That is to say, the charge retainability of the capacitor improves. Also, when the secondary internal supply voltage is set at a substantially constant value, the variation in sub-threshold current, resulting from the change in gate voltage of the access transistor of the memory cell, can be minimized. Accordingly, the capacitor can retain stored charges thereon almost completely even against the variation in external supply voltage.
In yet another embodiment, the power supply circuit may step down the external supply voltage to generate primary and secondary internal supply voltages as the internal supply voltages. The primary internal supply voltage may be lower than the external supply voltage. The secondary internal supply voltage may be approximately equal to an average of the absolute value of a threshold voltage of the access transistor and the primary internal supply voltage. The data lines may be supplied with the secondary internal supply voltage as a precharge voltage. And the word lines may be supplied with a ground voltage as a selected-state voltage.
In such an embodiment, a voltage, approximately equal to an average of the high- and low-level voltages on the data lines, is the precharge voltage for the data lines. This voltage is almost equal to an average of the capacitor voltage of a memory cell on which charges are stored and the capacitor voltage of the same memory cell on which no charges are stored. Accordingly, the variation in voltage on the data lines when stored charges are read out from a capacitor onto the data lines can have almost the same absolute value as the variation in voltage on the data lines when no charges are read out from the capacitor. For that reason, the read data can have its logical level determined accurately enough by the variation in voltage on the data lines with the read error minimized.
In this particular embodiment, a voltage representing the low level of the data lines is preferably the ground voltage.